View CY62168DV30_238712.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62168DV30 MoBL
16-Mbit (2048K x 8) Static RAM
Features
* Very high speed: 55 ns and 70 ns -- Wide voltage range: 2.20V - 3.60V * Ultra-low active power -- Typical active current: 2 mA @ f = 1 MHz -- Typical active current: 15 mA @ f = fmax * Ultra-low standby power * Easy memory expansion with CE1, CE2 and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Packages offered in a 48-ball FBGA addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins(A0 through A20). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). See the truth table for a complete description of read and write modes.
Functional Description[1]
The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 90% when
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
CE1 CE2 WE OE
Data in Drivers
I/O0 I/O1
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
2048K x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05329 Rev. *D
*
3901 North First Street
A17 A18 A19 A20
A16
A13 A14 A15
*
San Jose, CA 95134 * 408-943-2600 Revised September 14, 2004
CY62168DV30 MoBL
Pin Configuration[2]
FBGA
Top View 1 DNU 2 OE 3 A0 A3 A5 A17 DNU A14 A12 A8 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 6 CE2 A B C D E F G H
DNU DNU I/O0 VSS VCC I/O3 DNU A18 A A DNU I/O1 I/O2 DNU
CE1 DNU DNU I/O5 I/O6 DNU WE A11 I/O4 VCC VSS I/O7 DNU A19
Product Portfolio
Power Dissipation Operating ICC (mA) VCC Range (V) Product CY62168DV30L CY62168DV30LL Min. 2.2 2.2 Typ.[3] 3.0 3.0 Max. 3.6 3.6 Speed (ns) 55 70 55 70 2 4 f = 1 MHz Typ.[3] 2 Max. 4 f = fmax Typ.[3] 15 12 15 12 Max. 30 25 30 25 2.5 22 Standby ISB2(A) Typ.[3] 2.5 Max. 30
Notes: 2. DNU pins have to be left floating or tied to VSS to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05329 Rev. *D
Page 2 of 9
CY62168DV30 MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ........................................ -0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[4, 5] ......................... -0.3V to VCC(max) + 0.3V DC Input Voltage[4, 5] ......................-0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA) [6] -40C to +85C VCC[7] 2.2V - 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62168DV30-55 Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 VIH Input HIGH Voltage 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 GND < VI < VCC f = fMAX = 1/tRC f = 1 MHz Vcc = 3.6V, IOUT = 0mA, CMOS level IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOH = 2.1 mA 1.8 2.2 -0.3 -0.3 -1 -1 15 2 2.5 2.5 2.5 2.5 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 30 4 30 22 30 22 1.8 2.2 -0.3 -0.3 -1 -1 12 2 2.5 2.5 2.5 2.5 Typ.
[3]
CY62168DV30-70 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 25 4 30 22 30 22 A A V Typ.[3] Max. Unit V
Max.
V
VIL IIX IOZ ICC
Input LOW Voltage Input Leakage Current VCC Operating Supply Current Automatic CE Power-down Current - CMOS Inputs
V A A mA
Output Leakage Current GND < VO < VCC, Output disabled
ISB1
CE1 > VCC - 0.2V, CE2 < L 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, LL WE, ) CE1 > VCC - 0.2V, CE2 < L 0.2V, VIN > VCC - 0.2V or LL VIN < 0.2V, f = 0, VCC=3.6V
ISB2
Automatic CE Power-down Current - CMOS Inputs
Thermal Resistance
Parameter JA JC Description Thermal (Junction to Ambient) Resistance[8] Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board BGA 55 16 Unit C/W C/W
Thermal Resistance[8] (Junction to Case)
Notes: 4.VIL(min) = -0.2V for pulse durations less than 20 ns. 5.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6.TA is the "Instant-On" case temperature. 7.Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 100 s wait time after Vcc stabilization.. 8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05329 Rev. *D
Page 3 of 9
CY62168DV30 MoBL
Capacitance[8]
e
Parameter CIN COUT
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.)
Max. 8 10
Unit pF pF
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.50V 16600 15400 8000 1.2
3.0V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[8] tR[9] Description VCC for Data Retention Data Retention Current L VCC = 1.5V CE1 > VCC - 0.2V or CE2 <0.2V LL VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 Typ.[3] Max. 3.6 15 10 Unit V A A ns ns
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE VCC CE1 VCC(min) tCDR VDR > 1.5 V VCC(min) tR
or
CE2
Note: 9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
Document #: 38-05329 Rev. *D
Page 4 of 9
CY62168DV30 MoBL
Switching Characteristics Over the Operating Range [10]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[11, 12] WE HIGH to Low Z[11] 10 55 40 40 0 0 40 25 0 20 10 70 60 60 0 0 45 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[11] OE HIGH to High Z[11, 12] CE1 LOW and CE2 HIGH to Low Z[11] CE1 HIGH or CE2 LOW to High Z[11, 12] CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH or CE2 LOW to Power-Down 0 55 10 20 0 70 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 ns Max. Unit
Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05329 Rev. *D
Page 5 of 9
CY62168DV30 MoBL
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
[14, 15]
tRC
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE tPU SUPPLY CURRENT 50%
[13, 17, 18]
tHZOE tHZCE DATA VALID tPD 50% HIGH IMPEDANCE
ICC ISB
Write Cycle No. 1(WE Controlled)
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA
OE tSD DATA I/O See Note [19] tHZOE
Notes: 14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 17. Data I/O is high impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied.
tHD
VALID DATA
Document #: 38-05329 Rev. *D
Page 6 of 9
CY62168DV30 MoBL
Switching Waveforms (continued)
Write Cycle No. 2(CE1 or CE2 Controlled)
[13, 17, 18]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tHA
OE tSD DATA I/O VALID DATA
[19]
tHD
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATAI/O See Note [19] tHZWE VALID DATA tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X Inputs/Outputs High Z High Z Data Out (I/O0-I/O7) High Z Data in (I/O0-I/O7) Mode Deselect/Power-down Deselect/Power-down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (Icc) Active (Icc)
Document #: 38-05329 Rev. *D
Page 7 of 9
CY62168DV30 MoBL
Ordering Information
Speed (ns) 55 70 55 70 Ordering Code CY62168DV30L-55BVXI CY62168DV30LL-55BVXI CY62168DV30L-70BVXI CY62168DV30LL-70BVXI CY62168DV30L-55BVXI CY62168DV30LL-55BVXI CY62168DV30L-70BVXI CY62168DV30LL-70BVXI Package Name BV48B BV48B BV48B BV48B BV48B BV48B BV48B BV48B Package Type 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) Industrial Industrial Industrial Operating Range Industrial
Package Diagrams
48-Lead VFBGA (8 x 9.5 x 1 mm) BV48B
51-85150-*B
51-85178-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05329 Rev. *D
Page 8 of 9
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62168DV30 MoBL
Document History Page
Document Title: CY62168DV30 MoBL(R) 16-Mbit (2048K x 8) Static RAM Document Number: 38-05329 REV. ** *A *B *C *D ECN NO. 118409 123693 126556 132869 272589 Issue Date 09/30/02 02/05/03 04/24/03 01/15/04 See ECN Orig. of Change GUG DPM DPM XRJ PCI New Data Sheet Changed Advance Information to Preliminary Added package diagram Minor change: Change sunset owner from DPM to HRT Changed Preliminary to Final Updated Final data sheet and added Pb-free package. Description of Change
Document #: 38-05329 Rev. *D
Page 9 of 9

▲Up To Search▲

Price & Availability of CY62168DV30

	To Download CY62168DV30 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .